Methods for fabricating metal lines for back end of the line (BEOL) applications in semiconductor devices are well known in the art. For example, FIG. 1 illustrates a typical fabrication of two metal lines in BEOL semiconductor device 10 and involves patterning of a metal layer using is lithography and metal reactive ion etch (RIE) techniques. A bottom barrier blanket layer, such as a Ti or TiN layer, is deposited on top of interlevel dielectric 11. This bottom barrier blanket layer is followed by deposition of a high conductivity metal, usually A1 with 0.5% Cu. The high-conductivity layer is then covered by depositing a top barrier blanket layer, such as a Ti or TiN layer.
A photoresist layer is patterned into a mask (not shown) over portions of the layers in a known fashion. After photoresist exposure, the masking material (photoresist in this case) is removed in areas where the metal is to be removed by the RIE process. One such structure produced after the RIE process is shown in FIG. 1. As shown, the structure contains (1) metal line 12a sandwiched between top barrier 13a and bottom barrier 14a, and (2) metal line 12b sandwiched between top barrier 13b and bottom barrier 14b.
Following patterning of the final metal layer, a passivation layer (not shown) is deposited over the entire top surface of the wafer. This is an electrically insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging of the wafer. Thus, metal lines 12a and 12b are usually encapsulated by a dielectric deposition of oxides. These oxides may be deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or high density plasma (HDP) deposition.
It has been observed that voids may occur in the is metal lines due to some process imperfection. The voids may appear on one side of the metal line or on both sides of the metal line. It has been believed that these voids occur because of "undercut" conditions during the RIE process. Because the voids are imperfections in the metal lines, they contribute to decreasing the reliability of the semiconductor.
It is also known that dielectrics such as HDP, CVD, and PECVD oxides, used commonly in the semiconductor industry for BEOL passivation, exert compressive stress (expressed as a negative force pushing down) on the metal lines. The compressive stress may also be a factor in producing voids in the metal lines. The stress-induced voids also contribute to the reduced reliability of the semiconductor device.
The deficiencies of the conventional processes used to make metal lines in BEOL semiconductor devices show that a need still exists for a process which can reduce or eliminate the metal voids created in these metal lines after the metal layer has been deposited on the substrate.